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<div class="header">
  <div class="headertitle"><div class="title">PWM (Pulse Width Modulator)<div class="ingroups"><a class="el" href="group__group__hal__impl.html">CAT1 Implementation Specific</a></div></div></div>
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<h1><a class="anchor" id="section_hal_impl_pwm_compl_pins"></a>
Complementary PWM output</h1>
<p >The PWM HAL driver allows generation of a normal and an inverted output. PSoC™ devices support complementary pin pairs to which the normal and inverted signals can be routed. To identify the complementary pin for a given pin, open the PSoC™ device datasheet and navigate to the 'Multiple Alternate Functions' table. Each column represents an alternate function of the pin in the corresponding row. Find your pin and make a note of the tcpwm[X].line[Y]:Z. The complementary pin is found by looking up the pin against tcpwm[X].line_<b>compl</b>[Y]:Z from the same column. For example, the image below shows a pair of complementary pins (P0.0 and P0.1) identified by the tcpwm[0].line[0]:0 and tcpwm[0].line_compl[0]:0 mapping. These complementary pins can be supplied to <a class="el" href="group__group__hal__pwm.html#gacbeddfe75ccc849d27bec32ce010eceb">cyhal_pwm_init_adv</a> using <b>pin</b> and <b>compl_pin</b> parameters in any order.</p><div class="image">
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Complementary PWM pins</div></div>
<h1><a class="anchor" id="section_psoc6_pwm_resolution"></a>
PWM Resolution</h1>
<p >On CAT1 (PSoC™ 6) devices, not all PWMs hardware blocks are of the same resolution. The resolution of the PWM associated with a given pin is specified by the <code>TCPWM&lt;idx&gt;_CNT_CNT_WIDTH</code> macro (provided by cy_device_headers.h in mtb-pdl-cat1), where <code>&lt;idx&gt;</code> is the index associated with the <code>tcpwm</code> portion of the entry in the pin function table. For example, if the pin function is <code>tcpwm[1].line[3]:Z</code>, <code>&lt;idx&gt;</code> would be 1.</p>
<p >By default, the PWM HAL driver will configure the input clock frequency such that all PWM instances are able to provide the same maximum period regardless of the underlying resolution, but period and duty cycle can be specified with reduced granularity on lower-resolution PWM instances. If an application is more sensitive to PWM precision than maximum period, or if a longer maximum period is required (with correspondingly reduced precision), it is possible to override the default clock by passing a <a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__clock__t">cyhal_clock_t</a> instance to the <a class="el" href="group__group__hal__pwm.html#ga54a93c541bdbb3fce066a2af00d8b67f">cyhal_pwm_init</a> function with a custom frequency specified. See the <a class="el" href="group__group__hal__clock.html">Clock</a> HAL documentation for more details. </p>
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